With the extremely high rate of production and use of integrated circuits in computers and other types of digital module operations, designers have been increasingly aware that methods for testing and diagnosing the internal structure and operations of integrated chips is a necessary and important function.
Desirability of initiating standards for embedding logic circuitry into integrated chips has been proposed and developed by the IEEE committees which have proposed a boundary scan architecture designated IEEE 1149.1. This boundary scan architecture involves placing a chain of registers around the periphery of integrated circuits in order to allow the device input/output (I/O) to be controlled and observed by means of a four-wire serial scan bus. Thus, the registers for multiple devices can be connected in series to form a complete path through all the devices either completely within the integrated circuit chip or can also be used for providing a serial scan on an entire board holding integrated circuit devices.
The proposed IEEE 1149.1 standards define operations allowing a sampling of boundary values during "normal operation" in order to observe data flow and also to select a scan bypass register to provide a single-bit scan path through a device. Thus, as seen in the attached FIG. 6, the IEEE standard provides an integrated circuit (ICN) level test framework consisting of a four-wire Test Access Port (TAP) controller 7 and the related scan path architecture as shown in FIG. 6.
The Test Access Port (TAP) controller 7 receives external control inputs by means of a Test Clock (TCK) on line 7.sub.k and also a Test Mode Select (TMS) signals on line 7m. It then provides output control signals to the internal scan paths.
Absent the requirement for embedded testability, the normal integrated circuit logic would be represented by the block 8 where data could be fed in on line 6.sub.i and routed out on line 6.sub.o.
However, by adding in the auxiliary embedded logic into the chip, it is then possible to provide testability of the chip for integrity in addition to being able to readout the various state conditions of each of the logic circuits 8. As seen in FIG. 6, the scan path architecture will be seen to have a single serial instruction register 10 and two or more serial data registers 15 and 18. These are called Boundary Scan Registers (BSR). Thus, as seen in FIG. 6, the data registers 15, 18 are called a Boundary Scan Registers and the data register 16 is called a Scan Bypass Register.
The instruction register 10 and the Boundary Scan Data Registers 15 and 18 are connected in parallel between a serial TDI (Test Data Input) signal line 5 and a serial TDO (Test Data Output) signal on line 25.
The TDI input line 5 in FIG. 6 is connected directly to the serial inputs of the instruction register 10, and the Data Registers 15 and 18. The Test Data Output on line 25 (TDO) can receive its signals from several sources, namely: from the instruction register 10, from the bypass register 16 via multiplexer 22.sub.x and multiplexer 21.sub.x, or the test data output line 25 may receive data from the Boundary Scan Register 18 through multiplexer 22.sub.x and multiplexer 21.sub.x.
The selective control signals for the multiplexer 21.sub.x is supplied by the TAP (Test Access Port) controller 7. The selection control signals for the multiplexer 22.sub.x comes from the instruction register 10.
When "boundary testing" is not being performed, the Boundary Scan Registers 15 and 18 are "transparent" and out of the circuit, thus allowing the input signals and the output signals to pass to and from the Integrated Circuit (IC) logic 8.
However, during "boundary testing" in FIG. 6, the Boundary Scan Registers 15 and 18 will disable the normal flow of data between input 6.sub.i and output 6.sub.o in order to allow boundary signals of integrated circuit, IC 8, to be controlled and observed by means of scanning operations.
Thus, there is provided the ability to sample data passing through the I/O boundary of an integrated circuit or groups of integrated circuits, thus allowing the designers to take a snapshot of the logic states within the integrated circuit or within a group of integrated circuits on a printed circuit board without removing the board from its container.
The concept involved here is often called built-in testability (BIT). Thus, by providing the greater control and observability of the internal nodes in the normal Integrated Circuit (IC) logic 8, this allows a system to be tested much more efficiently with smaller test programs, shorter execution times and greater fault coverage. This efficiency can reduce the time and expense on test generation during verification or debug, thus allowing more rapid and more reliable testing.
In addition to checking the hardware, the enhanced accessibility of the "states" of the internal nodes can simplify application software testing and hardware/software integration. Thus, software designers can use the test bus 5 in FIG. 6 to download code in order to target various elements in the hardware and to monitor their response. With this increased observability, this makes it easier to sort out the hardware/software from integration problems. Thus, while many earlier systems required debug and testing to occur by means of pulling out suspected printed circuit boards or suspected integrated chips out of the system and putting in new ones in order to correct system problems in the field, in the presently described system, the maintenance can be carried out internally and diagnostically, thus to eliminate the necessity for carrying spare boards and IC chips which would be used for replacing defective boards and chips.
The designation JTAG refers to an architecture proposed by the Joint Test Action Group (JTAG) which specifies a four-wire test bus and boundary scan architecture for embedding around the logic circuitry of an integrated circuit chip. This enables the linking of integrated circuit logic to enable testing and diagnosis. These type built-in test features are specified in IEEE Standard 1149.1 (Test Standards Committee).